In conventional programmable logic devices (“PLDs”), including without limitation Field Programmable Gate Arrays (“FPGAs”), a programmable interconnect network (“routing fabric”) is constructed where fanout is provided by “forking” an output wire and fanin is provided with programmable multiplexers. Asynchronous circuits, which may be self-timed event driven circuits, may be difficult to implement in such a conventional interconnect network. Hence, it is desirable and useful to provide a programmable interconnect network more suitable for asynchronous circuits for ICs, including without limitation PLDs.